A memristor is an electrical component utilized to store data in a manner similar to that of an electrically erasable programmable read-only memory (EEPROM) cell, but differs from standard reprogrammable non-volatile memory cells in that a memristor utilizes only two terminals. That is, standard EEPROM cells typically utilize three (i.e., source, drain and control/select) terminals to implement reprogrammable memory operations. In contrast, memristors are required to perform both program/erase operations and readout operations using only two terminals. Typically, a memristor's electrical resistance is caused to increase by passing a program/erase current through the memristor in one direction, and caused to decrease by passing the program/erase current in the opposite direction. Once the memristor's resistance state is programmed (set) in this manner, the stored data (i.e., the programmed increased or decreased resistance state) remains non-volatilely fixed (stored) until it is overwritten (changed) by a subsequently applied program/erase current. Also similar to an EEPROM, the stored data bit can be determined during a readout operation by applying a read voltage across the memristor and measuring a read current passed through the memristor, where the amount of read current passing through the memristor is determined by the programmed resistance state. According to Leon Chua, the inventor of memristors, all two-terminal non-volatile memory devices based on resistance switching are memristors, regardless of the device material and physical operating mechanisms.
In the early synapses-related modeling, attempts were made to emulate memristor-type performance using floating gate technology, where EEPROM-type memory devices (cells) were connected in cross-point arrays to implement neuro-inspired circuits that model learning processes in biological systems. As used herein, the phrase “floating gate technology” refers to integrated circuit fabrication techniques utilized, for example, to produce EEPROMs and other floating gate MOSFET (FGMOS) field-effect transistors. Such floating gate transistors are similar to conventional MOSFETs, but drain-to-source currents are controlled by a gate structure made up of an electrically isolated (i.e., completely surrounded by oxide or other highly resistive material) block of doped polycrystalline silicon (polysilicon, or simply “poly”) capable of storing an applied charge for long periods of time. Floating gate technology employs the various programming mechanisms (e.g., Fowler-Nordheim tunneling and hot carrier injection) and associated circuit features to adjust (i.e., program or erase) the charge stored on floating gates.
Most attempts to implement synapses-related modeling based on floating gate technology utilize three-terminal EEPROM-type devices. Note that, although these floating gate devices were able to simulate memristor behavior, and were therefore sometimes referred to as “memristors”, they are technically not memristors due to their three (not two) terminals. Moreover, attempts to utilize three-terminal floating gate devices were deemed overly complicated due to the need to control the third terminal (i.e., the control gate in non-volatile memory (NVM) terminology), which made the synapses-related modeling circuit schematically difficult and costly. Such three-terminal devices were used by Bernard Widrow and Ted Hoffin in the first neuromorphic simulators named Adaline and Madaline. Examples of such devices can be found in IEEE Transactions on Neural Networks, 1992; 3(3), pp. 347-53, “Comparison of floating gate neural network memory cells in standard VLSI CMOS technology” by Durfee D. A, et al.
Some three-terminal EEPROM-type devices utilized in neural networks were fabricated using double-poly CMOS processes. FIG. 10 depicts a representative device of this type, and is similar to that disclosed in “A Single-Transistor Silicon Synapse”, Chris Diorio et al., (IEEE Transactions ED, vol. 43, No. 11, 1996). The disclosed device includes source and drain terminals, a third (control gate) terminal implemented using a second polysilicon (POLY2) structure disposed over the floating gate, which is implemented using a first polysilicon (POLY1) structure. These devices are programmed by channel hot electrons and erased by Fowler-Nordheim tunneling generated at the locations indicated in FIG. 10. The authors of the above-mentioned paper disclosed a two-dimensional synaptic array in which each three-terminal EEPROM-type device of FIG. 10 formed one synapse of the array. In addition to the devices not being memristors (i.e., because they have three terminals), and in addition to their fabrication using a complicated double-poly fabrication technology, the three-terminal EEPROM-type device of FIG. 10 encountered array limitations in that row synapses shared a common drain line, so tunneling at one synapse caused undesired tunneling and hot carrier injection at other row synapses.
FIG. 11 shows an exemplary two-terminal EEPROM-type floating gate cell similar to those disclosed, for example, in “EEPROM MEMORY CELL AS A MEMRISTIVE COMPONENT” by Herman Kohlstedt et al., (Universitat Zu Kiel); International Application No. WO2013178730 (also published as German Application No. DE102012209336). The disclosed two-terminal device utilizes a floating gate FG, and is configured as a memristor by way of connecting a control gate CG to the drain terminal D. The floating gate FG allows the respective channel resistance value taken last to be preserved even when no more external voltage is applied at the terminal connections C1 and C2.
FIG. 12 is a simplified diagram depicting two-terminal memristor elements disposed in a cross-point array configuration similar to that utilized in two-dimensional synaptic arrays for synapses-related modeling. The two-terminal memristor elements ME (indicated by rectangles) have drain terminals respectively connected to an associated bit (row) lines BL1 to BL3, and source terminals respectively connected to an associated word (column) lines WL1 to WL3.
Based on practical experience, the present inventors understand that cross-point arrays generated using conventional two-terminal EEPROM-type devices (e.g., see FIG. 11) encounter over-erase problems during erase operations and require the use of high-voltage readout operations, where both of these problems lead to read disturb issues that prevent reliable synapses-related modeling.
Referring to FIG. 12, over-erase is caused by way directly connecting the drain terminals of the memristor elements ME to associated shared bit lines BL1 to BL3 during erase operations, and results in a reduction of the Vt of the over-erased memristor element below 0.5V. During a typical programming operation, the drain electrode/terminal of a target element (e.g., element TME) is directly connected to a high programming voltage source by way of its associated bit line (e.g., bit line BL2), and during erase operations the element's source terminal is connected to a high voltage by way of its associated word line (e.g., a high voltage on word line WL2 is applied to the source terminal of target element TME). Unless the drain terminal of target element TME is isolated during the erase operation, an uncontrollable erase mode may occur that can result in an over-erase condition, which can lead to degradation or even complete failure of the device. That is, the uncontrollable erase mode occurs when the element's floating gate reaches a fully erased state during an erase operation, and channel electrons generate secondary holes that enter the floating gate, producing an undesirable further reduction of the stored charge that produces a threshold voltage below desirable levels (e.g., below 0.5V). This uncontrollable erase mode cannot be prevented unless the drain electrode is disconnected or otherwise isolated during the erase operation. However, because the drain terminal is directly connected to an associated bit line in order to facilitate programming operations, and because a third terminal is not available to selectively isolate the drain terminal during erase operations, memristor elements ME are subject to over-erase. The present inventors encountered this over-erase problem when experimenting with EEPROM configurations similar to those of FIG. 11 (e.g., those disclosed in co-owned U.S. Pat. No. 7,800,156), and determined that over-erase caused the memory device's threshold voltage to be decreased below 0.5V.
High-voltage readout operations, typically of the order of 2V to 3V, are required by conventional two-terminal EEPROM-type devices (e.g., see FIG. 11) because there is no separate control gate (as in EEPROM memories) to avoid over-erase, so both program/erase and readout operations must be performed through the same two-terminal transistor structure. Because the transistor structure must be sufficiently robust to exclude sneak (leakage) currents in the array, the transistor structure's threshold voltage (e.g., when erased) is also relatively high (e.g., 1.5V to 2.5V), thereby requiring readout voltages in the range of 2V to 3V. These high readout voltages are generated across a target element (e.g., central memristor element TME in FIG. 12) by way of applying two signals (e.g., 3V and 0V) respectively to associated bit line BL2 and associated word line WL2, whereby a charge stored on target memristor element TME can be determined by measuring a resulting read current IREAD generated on associated word line WL2. However, the low Vt can lead to sneak currents through other memristor elements, such memristor element OEME in FIG. 12, that can prevent accurate readout of a target memristor element. For example, as indicated in FIG. 12, during readout of target memristor TME, if neighboring memristor element OEME is over-erased, a sneak current ISNEAK can be generated through over-erased element OEME by way of (intermediate) elements IME1 and IME2 such that sneak current ISNEAK flows on bit line BL2, thereby preventing accurate readout of the programmed/erased state of target element TME by corrupting read current IREAD.
Neuromorphic engineering, also known as neuromorphic computing, is a concept developed by Carver Mead in the late 1980s, and involves the use of very-large-scale integration (VLSI) systems containing electronic analog circuits to mimic neuro-biological architectures present in the nervous system. In recent times the term neuromorphic has been used to describe analog, digital, and mixed-mode analog/digital VLSI circuits and software systems that implement models of neural systems (for perception, motor control, or multisensory integration). The implementation of neuromorphic computing has been implemented on the hardware level by neuromorphic circuits. A key aspect of neuromorphic engineering is understanding how the morphology of individual neurons, circuits, applications, and overall architectures creates desirable computations, affects how information is represented, influences robustness to damage, incorporates learning and development, adapts to local change (plasticity), and facilitates evolutionary change. Neuromorphic engineering is an interdisciplinary subject that takes inspiration from biology, physics, mathematics, computer science and electronic engineering to design artificial neural systems, such as vision systems, head-eye systems, auditory processors, and autonomous robots, whose physical architecture and design principles are based on those of biological nervous systems.
To date, most VLSI circuits developed for neuromorphic systems relied on floating gate memristors or arrays of three-terminal memristor-emulating cells, such as those described above, and were therefore subject to the limitations mentioned above. More recently, various new types of memristors have been introduced, including Phase-Change Memory (PCM), and Resistive Random-Access Memory (RRAM or ReRAM), all of which being referred to as memristive elements or memristors. Though allowing small cell footprints, these memristor technologies are still not fully mature. In particular, the arrays of interconnected resistive memory two-terminal devices require special additional rectifying elements in each of the memristor cells. Otherwise, such arrays exhibit sneak currents (i.e., stray currents due to leakage). Memory arrays using ReRAM memristors also have reliability (endurance and retention) limitations.
What is needed is a memristor suitable for neuromorphic simulations and other bio-inspired modeling systems that utilizes the benefits of floating gate technology while overcoming the above-mentioned problems associated with implementing conventional memristor devices in cross-point array configurations. What is particularly needed is a two-terminal, floating gate (EEPROM-type) memristor capable of implementing reliable floating gate program/erase operations while avoiding the over-erase problems associated with conventional approaches, and also capable of performing readout operations at voltages low enough to avoid the parasitic programming (read-disturb) problems associated with conventional approaches. What is preferably needed is a solution achieving the above that can also be implemented using low-cost standard single-poly semiconductor fabrication (e.g., CMOS) technology.